1. Address Generator

One of the common patterns that leads to long critical paths in designs on the FPGA are counters and comparisons against counters. This package contains a module for generating the sequence of addresses used by a memory read or write burst, along with a field indicating the last beat of the burst.

struct AddressGenerator::AddrBeat#(numeric type addrWidth)
addr → Bit#(addrWidth)

The address for this beat of the request.

bc → Bit#(BurstLenSize)
tag → Bit#(MemTagSize)
last → Bool
interface AddressGenerator::AddressGenerator(numeric type addrWidth, numeric type dataWidth)
request → Put#(PhysMemRequest#(addrWidth))

The interface for requesting a sequence of addresses.

addrBeat → Get#(AddrBeat#(addrWidth))

The interface for getting the address beats of the burst. There is one pipeline cycle from the reuqest to the first address beat.

module AddressGenerator::mkAddressGenerator → (AddressGenerator#(addrWidth, dataWidth)

Instantiates an address generator.