12. Portal Package

12.1. PipePortal Interface

interface Portal::PipePortal(numeric type numRequests, numeric type numIndications, numeric type slaveDataWidth)
messageSize(Bit#(16) methodNumber) → Bit#(16)

Returns the message size of the methodNumber method of the portal.

requests → Vector#(numRequests, PipeIn#(Bit#(slaveDataWidth)))
indications → Vector#(numIndications, PipeOut#(Bit#(slaveDataWidth)))

12.2. MemPortal Interface

interface Portal::MemPortal(numeric type slaveAddrWidth, numeric type slaveDataWidth)
slave → PhysMemSlave#(slaveAddrWidth,slaveDataWidth)
interrupt → ReadOnly#(Bool)
top → WriteOnly#(Bool)
function Portal::getSlave(MemPortal#(_a, _d) p) → PhysMemSlave(_a,_d)
function Portal::getInterrupt(MemPortal#(_a, _d) p) → ReadOnly#(Bool)
function Portal::getInterruptVector(Vector#(numPortals, MemPortal#(_a, _d)) portals) → Vector#(16,ReadOnly#(Bool))

12.3. ShareMemoryPortal Interface

interface Portal::SharedMemoryPortal(numeric type dataBusWidth)

Should be in SharedMemoryPortal.bsv

readClient → MemReadClient(dataBusWidth)
writeClient → MemWriteClient#(dataBusWidth)
cfg → SharedMemoryPortalConfig
interrupt → ReadOnly#(Bool)

12.4. ConnectalTop Interface

interface Portal::ConnectalTop(numeric type addrWidth, numeric type dataWidth, type pins, numeric type numMasters)

Interface ConnectalTop is the interface exposed by the top module of a Connectal hardware design.

slave → PhysMemSlave#(32,32)
masters → Vector#(numMasters,PhysMemMaster#(addrWidth, dataWidth))
interrupt → Vector#(16,ReadOnly#(Bool))
leds → LEDS
pins → pins

12.5. StdConnectalTop Typedef

typedef Portal::StdConnectalTop(numeric type addrWidth) → ConnectalTop#(addrWidth,64,Empty,0)

Type StdConnectalTop indicates a Connectal hardware design with no user defined pins and no user of host shared memory. The “pins” interface is Empty and the number of masters is 0.

typedef Portal::StdConnectalDmaTop(numeric type addrWidth) → ConnectalTop#(addrWidth,64,Empty,1)

Type StdConnectalDmaTop indicates a Connectal hardware design with no user defined pins and a single client of host shared memory. The “pins” interface is Empty and the number of masters is 1.