# 1. Makefile.connectal¶

A Connectal design imports Makefile.connectal into its Makefile in order to drive the build.

A number of variables are used to control the build and parameters of the design.

## 1.1. Environment Variables¶

CONNECTALDIR

Points to the location where Makefile.connectal and the connectal tools are installed.

## 1.2. Make Variables Defining the Application¶

BOARD

This is typically set from the suffix of the build target, e.g., make build.zedbard defines BOARD=zedboard.

INTERFACES

Specifies for which interfaces to generate c/c++/bsv proxies and wrappers.

NUMBER_OF_MASTERS

Number of DMA masters in the design. Defaults to 1.

PIN_TYPE

BSV interface of exported pins. Defaults to Empty. BSV type bsv:typedef::PinType is defined from PIN_TYPE.

PIN_TYPE_INCLUDE

Which BSV package to import to get the declaration of PIN_TYPE.

PINOUT_FILE

Which pin usage JSON files to pass to makefilegen.py as :option::–pinout options.

BSVFILES

Lists the BSV files to scan when processing INTERFACES.

CPPFILES

Lists the C/C++ files that implement the application.

CPPFILES2

Lists the C/C++ files that implement the (optional) second executable of an application. For example, a daemon that coordinates access to the hardware.

PORTAL_DUMP_MAP

Specifies the option to provide to pcieflat to annotate PCIe traces with portal numbers and method names. Uses generatedDesignInterfaceFile.json.

## 1.3. Auto Top¶

S2H_INTERFACES
H2S_INTERFACES
MEM_READ_INTERFACES
MEM_WRITE_INTERFACES

## 1.4. Controlling the Build¶

CONNECTALFLAGS

Flags to pass to makefilegen.py. See _invocation_makefilegen.py for its options.

V

Controls verbosity of the build. V=1 for verbose.

USE_BUILDCACHE

Define USE_BUILDCACHE=1 to use buildcache. Except fpgamake seems to use buildcache anyway.

BUILDCACHE

Location of buildcache script.

BUILDCACHE_CACHEDIR

To specify an alternate location for the buildcache cache files.

IPDIR

Specifies into which directory to generate IP cores. This allows generated cores to be shared between designs when the FPGA part and core parameters match.

MAIN_CLOCK_PERIOD

Bound to the clock period, in nanoseconds, of the clock domain of mkConnectalTop.

Defaults to 8ns for vc707 and kc705.

Defaults to 10ns for zedboard.

Defaults to 5ns for zc706.

DEFAULT_DERIVED_CLOCK_PERIOD

Bound to the default clock period, in nanoseconds, of the derived clock provided via HostInterface to mkConnectalTop. Defaults to half the period, twice the frequency of the main clock.

DERIVED_CLOCK_PERIOD

Bound to the clock period, in nanoseconds, of the derived clock provided via HostInterface to mkConnectalTop. Defaults to DEFAULT_DERIVED_CLOCK_PERIOD.

BURST_LEN_SIZE

Controls width of fields specifying memory request burst lengths. Defaults to 8.

RUNPARAM

Specifies the name or IP address of the machine on which to run the application, e.g.:

make RUNPARAM=192.168.168.100 run.android


## 1.5. Top Level Make Targets¶

build.%

Builds software and bitfile for the specified board name, e.g.,:

make build.zedboard

run.%

Programs the FPGA and runs the application using the build for the specified board name. Uses :make:var:RUNPARAM. For example,:

make RUNPARAM=sj10 run.vc707


## 1.6. Intermediate Make Targets¶

verilog

Runs the build up through generation of verilog from BSV. Requires BOARD to be defined.

bits

Generates the FPGA bit file from the design. Requires BOARD to be defined.

bsim

For BOARD=bluesim, generates the simulation executable.

xsim

For BOARD=xsim, generates the simulation executable.

android.exe

Builds the software executable for boards using Android.

ubuntu.exe

Builds the software executable for boards using Ubunto/CentOS.

bsim_exe

Builds the software executable for bluesim.

gentarget

This step creates the board directory and Makefile.

prebuild

Additional steps needed before making verilog, etc. Use this target for dependences such as constraint file and IP core generation that need to be run before the design is built. This is a :: dependence, so you can specify it multiple times.